The present invention relates to a pipelined information processing apparatus and, more particularly, to a pipelined information apparatus for simultaneously executing a plurality of instructions.
In a conventional pipelined instruction control circuit, different functions are assigned to the respective stages so that instructions to be processed successively flow in the instruction control circuit without data determination. Various resources for a computer are then checked (e.g., checking of register interference conditions and contention of write paths to general registers). When all the execution conditions are satisfied, an execution command is output.
In order to successively execute instructions, the above-described instruction control circuit has control information corresponding to instructions which can be simultaneously executed. A condition as to whether or not an instruction can be executed when it passes through a certain stage is set as a flag of the control information. The instruction flows through the stage in the instruction control circuit in accordance with the state of the flag.
Furthermore, assume that in the instruction control circuit, the result of a preceding instruction is not stored in a general register, and a successive instruction for updating the general register flows to a stage in the instruction control circuit. In this case, even if the result of the preceding instruction is not stored in the general register, the successive instruction can be executed without being stopped at the stage in the instruction control circuit by inhibiting the preceding instruction from being written in the general register.
In the above instruction control circuit, however, if an instruction string is designed such that an instruction (the branch failure side) subsequent to a branch instruction uses the content of the same general register as that for storing the result of an instruction preceding the branch instruction, and a branch success is made by the branch instruction, the instruction subsequent to the branch success uses the result of the instruction preceding the branch instruction which is stored in the general register.
For this reason, if the result of the preceding instruction is not obtained yet, execution of an instruction which uses the result of the subsequent instruction must be suspended until the result of the preceding instruction is determined. That is, execution of the branch instruction is suspended until all the data determination preceding the branch instruction is completed at the branch instruction.
A conventional apparatus will be described below with reference to the accompanying drawings.
FIG. 2 shows an instruction string designed such that when a branch success is made, an instruction at a branch destination waits for determination of data provided before the branch instruction. FIG. 4 shows a conventional instruction control circuit. FIG. 5 shows a case wherein the instruction string shown in FIG. 2 is executed by the conventional instruction control circuit shown in FIG. 4.
Referring to FIG. 4, an instruction register 1 receives instructions and operands from an instruction supplying circuit, and supplies them to an instruction register 2. The instruction registers 1 and 2 are controlled by control signals from an instruction stage control circuit 4 and a conventional data determination control circuit 5a (corresponding to a portion enclosed with a dotted line in FIG. 4).
A general register write number holding register 6 is used when a write instruction with respect to a general register is to be executed. The register 6 has n entries (three entries in this case) and serves to store the number of a general register for which a write operation is performed. The register 6 stores such a number in response to a storage entry number signal 101 which is output when the value of the operand x in the instruction register 1 is transferred to the instruction register 2.
A compare circuit 7-1 detects a coincidence between the operands x respectively stored in the general register write number holding register 6 and the instruction register 1, and stores the value of the operand x in an identical register update stack number holding register (having a 3-bit arrangement in this conventional apparatus) 8. Compare circuits 7-2 and 7-3 detect coincidences between operands y and between operands z respectively stored in the general register write number holding register 6 and the instruction register 1. AND circuits 9-1 and 9-2 then logically AND the values of the operands y and z with a value obtained by inverting the value in the identical register update register number holding register 8 using an inverter 20. The resultant values are respectively stored in preceding instruction data use information holding registers 10-1 and 10-2 (each having a 3-bit arrangement in this conventional apparatus, the 3 bits of the register 10-1 indicating entries 1, 2, and 3 on the y operand side, and the 3 bits of the register 10-2 indicating entries 1, 2, and 3 on the z operand side).
A data undetermination information holding register 21 stores the information of the storage entry number signal 101, and is operated to reset an entry bit in which "1" is set when an OR circuit 16 logically ORs the value obtained by the compare circuit 7-1 with a reset number signal 104 as the OR product of an entry reset number signal 102 for canceling an instruction on an instruction stage upon a branch success, and a reset signal (data determination entry number signal 103) corresponding to a data determination entry.
Subsequently, an OR circuit 19 logically ORs the values of the preceding instruction data use information holding registers 10-1 and 10-2 with a value obtained by masking the value in the data undetermination information holding register 21 with the reset number signal 104 (which is performed by an inverter 17 and AND circuits 18-1 and 18-2). If the resultant value is "1", an instruction register 2 hold 1 signal 108 which is logically ORed with an instruction register 2 hold 2 signal 109 by an OR circuit 14. As a result, an instruction register 2 hold signal 105 is enabled and held in the instruction register 2.
When a branch instruction is supplied to the instruction register 1, a branch instruction register 1 signal 107 is transmitted to the instruction stage control circuit 4. The circuit 4 then outputs the instruction register 2 hold 2 signal 109 to hold the instruction in the instruction register 2 at the next timing. As a result, the instruction is held in the instruction register 2.
When the instruction passes through the instruction register 2, an instruction execution command is output.
FIG. 2 shows an instruction string designed such that a branch instruction is successfully executed, and current determination information data is lost.
Assume that a 3-operand instruction is used, and the three operands are respectively called operands x, y, and z, and that data are basically read out from general registers designated by the operands y and z to be calculated, and the calculation result is stored in a general register designated by the operand x.
Referring to FIG. 2, an instruction 1 indicates that data is loaded from a memory of number 100 into a general register of number 10. Similarly, an instruction 2 indicates that if the content of a general register of number 5 is 0 or less, control branches to an instruction of IC=500 (in this case, it is assumed that the instruction of IC=500 corresponds to an instruction 4. An instruction 3 indicates that the contents of general registers of numbers 8 and 9 are multiplied together, and the product is stored in the general register of number 10. An instruction 4 indicates that the content of the general register of number 10 is added to that of a general register of number 15, and the sum is stored in a general register of number 20.
FIG. 5 is a timing chart obtained when the instruction string in FIG. 2 is executed by the conventional apparatus in FIG. 4.
At timing 1, the instruction 1 is set in the instruction register 1. At timing 2, since the instruction 1 is an instruction to store the resultant data in the general register of number 10, "10" is set in the entry 1 of the general register write number holding register 6, and the instruction 1 is transferred to the instruction register 2. Upon setting of the instruction 1 in the entry 1, "100" is set the data undetermination information holding register 21, and the instruction 2 is newly set in the instruction register 1.
In addition, at timing 2, since the instruction in the instruction register 1 is a branch instruction, a branch instruction register 1 signal is transmitted to the instruction stage control circuit 4. The instruction 2 is held in the instruction register 2 in response to the instruction register 2 hold signal 105 output from the instruction stage control circuit 4 at timing 3.
The successive instruction 3 is held in the instruction register 1 in response to a register holding signal output from the instruction stage control circuit 4. From timing 5 to timing 17, no change occurs in the respective registers.
At timing 18, after the instructions 3 and 2 are respectively held in the instruction registers 1 and 2, when a signal (data determination signal) for determining that the result of the instruction 1 is stored in the general register of number 10 is supplied, all the data determination signals have been output. As a result, the instruction register 2 hold signal 105 is canceled. At the same time, the register holding signals output from the instruction stage control circuit 4 to the instruction registers 1 and 2 are canceled. Hence, at timing 20, the instruction in the instruction register 1 is transferred to the instruction register 2. An execution command is output with respect to the instruction 2 in the instruction register 2.
Since the instruction 3 is an instruction to store the resultant data in the general register of number 10, "10" is set in the entry 1. At the same time, "100" is set in the data undetermination information holding register 21.
At timing 21, since the instruction 4 is an instruction to store the resultant data in the general register of number 20, "20" is set in the entry 2 of the general register write number holding register 6.
In addition, since the operand y of the instruction 4 indicates the data which is read from the general register of number 10, the value in the general register write number holding register 6 and the values of the operands y and z in the instruction register 1 are compared with each other by the compare circuits 7-2 and 7-3 to detect a coincidence. Since values "100" and "000" are set for the operand y and z and are respectively supplied to the AND circuits 9-1 and 9-2, "100" and "000" are respectively stored in the preceding data use information holding registers 10-1 and 10-2. At the same time, "1" is set in the entry 2 of the data undetermination information holding register 21, and "110" is stored in the register 21.
At this time, since the AND product of the value ("110") of the data undetermination information holding register 21 and the values ("100" and "000") of the preceding instruction data use information holding registers 10-1 and 10-2 is not "0", the OR product thereof obtained by the OR circuit 19 becomes "1". As a result, at timing 22, the data in the instruction register 2, i.e., the instruction 4, is held in response to the instruction 2 hold signal 105.
At timing 22, since it is determined that the branch instruction 2 has succeeded, the reset number signal 104 is output to cancel the instructions 3 and 4 on the branch failure side (i.e., the reset number signal 104 is output to the entries 1 and 2 at which the instructions 3 and 4 are registered). As a result, the instruction 4 is removed from the instruction register 2.
When the branch success is made, the instruction 4 is supplied from the instruction supplying circuit at timing 31. At timing 32, the instruction 4 is executed.
In the above-described conventional pipelined instruction control scheme, until a success or failure of a branch instruction is determined, control information for a successive instruction is stored in an instruction control unit. For this reason, the result of an instruction (on the branch failure side) subsequent to the branch instruction is stored in the same general register as that for storing an instruction preceding the branch instruction. In this case, if an instruction string is designed such that an instruction subsequent to a branch instruction uses the result stored in the general register, and a branch success is made by the branch instruction, the instruction subsequent to the branch success inevitably uses the result stored in the general register which is stored prior to the branch instruction. If, therefore, the result of the instruction has not been obtained yet, execution of the subsequent instruction which uses the result of the preceding instruction must be suspended until the result of the instruction is determined. Since data determination for all the instructions preceding the branch instruction is completed at the branch instruction, execution of the branch instruction is inevitably delayed.